(1) Caches are useful when two or more components need to ex-change data, and the components perform transfers at differing speeds.
(2) Caches solve the transfer problem by providing a buffer of intermediate speed between the components. If the fast device finds the data it needs in the cache, it need not wait for the slower device. The data in the cache must be kept consistent with the data in the components. If a component has a data value change, and the datum is also in the cache, the cache must also be updated.
(3) This is especially a problem on multiprocessor systems where more than one process may be accessing a datum.
(4) A component may be eliminated by an equal-sized cache, but only if:
(a) the cache and the component have equivalent state-saving capacity (that is, if the component retains its data when electricity is removed, the cache must retain data as well),
(b) the cache is affordable, because faster storage tends to be more expensive.
(1) An interrupt is a hardware-generated change-of-flow within the system.
(2)An interrupt handler is summoned to deal with the cause of the interrupt; control is then returned to the interrupted context and instruction.
(3) A trap is a software-generated interrupt. An interrupt can be used to signal the completion of an I/O to obviate the need for device pooling.
(4) A trap can be used to call operating system routines or to catch arithmetic errors.
(1) CPU tells device what to do -- write to control register.
A device controller is a part of a computer system that makes sense of the signals going to, and coming from the CPU.
(2) Both of them are the devices what can control OS.
An interrupt cycle is a memory fetch sequence generated in response to the interrupt.
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