1.(一)Caches are useful when two or more components need to ex-change data, and the components perform transfers at differing speeds.
(二)Caches solve the transfer problem by providing a buffer of intermediate speed between the components.
(三)If the fast device finds the data it needs in the cache, it need not wait for the slower device. The data in the cache must be kept consistent with the data in the components.
If a component has a data value change, and the datum is also in the cache, the cache must also be updated.
This is especially a problem on multiprocessor systems where more than one process may be accessing a datum.
(四)A component may be eliminated by an equal-sized cache, but only if:
(a) the cache and the component have equivalent state-saving capacity
(that is, if the component retains its data when electricity is removed, the cache must retain data as well),
(b) the cache is affordable, because faster storage tends to be more expensive.
2.(一)The purpose of interrupts is to alter the flow of execution in response to some event.
(二)An interrupt is triggered in hardware and a trap is triggered in software.
(三)User programs can generate traps intentionally.
(四)They may want to interact with some I/O which requires a system call.
3.(一)CPU:A CPU is like a light switch and has two basic functions OFF and ON.
which brings us to binary all those 0's and 1's the only language the CPU
understands the 0 being OFF and the 1 being ON there are millions of switches
inside the CPU moving from OFF to ON millions of times a second processing all
the information you give it.
device controller:1.Stops and starts the activity of the peripheral device.
2.Generate error checking code.
3.Checks the error in the data recieved from the interface.
4.Abort that command which have errors.
5.Retry the command having an error.
6.Recieves the control signals from the interface unit.
7.Convert the format of the data .
8.Checks the status of the device.
(二)interprets commands before executing them.
4.A device asserts the interrupt signal at a hardwired interrupt level.
->The processor registers the interrupt and waits to finish the current instruction execution.
->Once the current instruction execution is completed, the processor initiates the interrupt handling by saving the current register contents on the stack.
->The processor then switches to supervisor mode and initiates an interrupt acknowledge cycle.
->The interrupting device responds to the interrupt acknowledge cycle with the vector number for the interrupt.
->Processor uses the vector number obtained above and fetches the vector.
->The address found at the vector is the address of the interrupt service routine (ISR) for the interrupting device.
->After the ISR routine has performed its job, the ISR executes the "return from interrupt" instruction.
->Execution of the "return from interrupt" instruction results in restoring the processor state. The processor is restored back to user mode.