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王同學 作品集 分享經驗 10/14 10/8OS作業

10/14 10/8OS作業
作品名稱 10/8OS作業
日期 10/14
課程名稱 作業系統
指導教師 劉艾華

1.
Caches are useful when two or more components need to ex-change data, and the components perform
transfers at differing speeds. Caches solve the transfer problem by providing a buffer of intermediate
speed between the components. If the fast device finds the data it needs in the cache, it need not wait
for the slower device. The data in the cache must be kept consistent with the data in the components.
If a component has a data value change, and the datum is also in the cache, the cache must also be updated.
This is especially a problem on multiprocessor systems where more than one process may be accessing a datum.
A component may be eliminated by an equal-sized cache, but only if:
(a) the cache and the component have equivalent state-saving capacity (that is, if the component retains
its data when electricity is removed, the cache must retain data as well),
and
(b) the cache is affordable, because faster storage tends to be more expensive.


2.
An interrupt is a hardware-generated change-of-flow within the system. An interrupt handler is summoned
to deal with the cause of the interrupt; control is then returned to the interrupted context and instruction.
A trap is a software-generated interrupt. An interrupt can be used to signal the completion of an I/O to
obviate the need for device polling. A trap can be used to call operating system routines or to catch arithmetic errors.

3.
A device controller is a part of a computer system that makes sense of the signals going to, and coming from the CPU.Any
device connected to the computer is connected by a plug and socket, and the socket is connected to a device controller.
It functions as a bridge between the device and the operating system.The electrical part of an I/O device is known as a
device controller and can take the form of a chip on personal computers.

4.
Direct Memory Access (DMA) and Interrupt Handling. In this series on hardware basics, we have already looked at read and write bus cycles.

更新日期:2015/10/15 上午 07:05:30